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Primer: Elements of Proc. Architecture. The H/S Interplay

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Dan Negrut

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Unread post Sat Aug 24, 2013 9:54 am

Primer: Elements of Proc. Architecture. The H/S Interplay

Please post here comments regarding the ME/ECE/CS/EMA 759 "Primer: Elements of Processor Architecture. The Hardware/Software Interplay."
I'm particularly interested in mistakes and things that were too vague to be useful.

Thank you very much for taking the time.
Dan
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f13-759-biondo

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Unread post Wed Sep 11, 2013 11:20 am

Re: Primer: Elements of Proc. Architecture. The H/S Interpla

Comments from the first 27 pages or so:

I am one of the engineering physics students so I have a fairly naive perspective on processor architecture. For the most part I have found this primer to be both clear and helpful. I have only a few suggestions so far:
  • Add a glossary. The acronyms (especially register types) are numerous and keeping track of them takes some page-turning.
  • Be consistant in notation: in Example 1.4 (page 21) register names are in courier font (as they are when they are introduced), but this is not the case in Example 1.5. This is not the biggest deal but as a reader when I come by this I usually spend time considering if this is done for a reason or not.
  • In Figure 13 (page 32) it is not obvious which portions of the memory hierarchy are contained within the processor.
I have also found some typos, which I can list here upon request (though I pressume you are more interested in high-level suggestions at this point).
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Dan Negrut

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Unread post Wed Sep 11, 2013 2:53 pm

Re: Primer: Elements of Proc. Architecture. The H/S Interpla

Elliot - thanks for your input, much appreciated.
Going back to your points:
* i won't be able to work on the glossary right now. I plan to do so though (a bit of a time black hole)
* i'm trying to be consistent, but obviously i'm missing many spots. i took care of Example 1.5. Please keep sending me suggestions for correction
* took care of it

Yes, please send me any typos you find, that's very helpful.

I updated the document based on your feedback and posted a new version on the course website.

thanks again.
Dan
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f13-759-biondo

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Unread post Wed Sep 11, 2013 3:13 pm

Re: Primer: Elements of Proc. Architecture. The H/S Interpla

The notation used below is "page:line", where line can be negative to denote indexing from the bottom of the page.
  • 5:-4 "once GPU card" -> "one GPU card"
  • 9:12 "$s3" -> "$s4"
  • 20:-10 "encounter" -> "encountered"
  • 21:13 "from where the R name" -> reword
  • 22:-8 "which operate" -> "which they operate"
  • 23:-9 "saw t through" -> "saw through" or reword
  • 24:14 "reported in square brackets" -> you do not actually do this
  • 25:-8 "thing g" -> "thing"
  • 28:5 "quite" -> reword
  • 30:15 "a jumped" -> "a jump"
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Dan Negrut

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Unread post Wed Sep 11, 2013 5:16 pm

Re: Primer: Elements of Proc. Architecture. The H/S Interpla

Awesome - thanks, Elliot.
You went beyond page 27 :-)
Dan
P.S. I updated again the document on the course webpage.
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f13-759-nsubramania2

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Unread post Thu Sep 12, 2013 1:44 am

Re: Primer: Elements of Proc. Architecture. The H/S Interpla

The document looked fairly neat and understandable. It had the flow, easy to follow. :)

Below, I have listed a few errors and typos that seemed substantial. I hope they are correct.

Page-8 Para-2 Line-2

"The collection of instructions a processors is expected to know how to carry out is called its instruction set " means correct if put this way - "The collection of instructions a processor is expected to know to carry out a process is called its instruction set"

Page-19 Para-4 Line-1
Typo : "MDF" that should be "MDR" which is the Memory Data Register. There is no MDF register.

Page-20 Para-1 Line-7
I reckon it should be 'right' "operation" signal and not 'write' "operation" signal.

Page-23 Para-1 Line-4
"might simply be send" should be "might simply be sent", I believe.

Page-23 Para-2 Line-9
"And as such, since with each tick a new product is finished." should be "And as such, with each tick a new product is finished.". "since" seems misplaced.

Page-24 Para-1 Line-9
"one vehicle that might one of three types" should be "one vehicle that might be one of three types"

Best. :)
- Naveen
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Dan Negrut

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Unread post Thu Sep 12, 2013 8:28 am

Re: Primer: Elements of Proc. Architecture. The H/S Interpla

Naveen - Thanks for the feedback, very useful. Here's my feedback to your feedback.

I changed that paragraph that included the ISA discussion to
"The “add” instruction above is one of several low level; i.e., elementary, instructions that the processor can be demanded to carry out. The collection of these low level instructions makes up the instruction set of the processor and along with it goes the concept of instruction set architecture (ISA). The ISA defines the instruction set but also a set of data types that go along with these instructions, a set of registers for data storage, the memory architecture, and protocols for interrupting the execution (interrupts and exception handling). Adopting an ISA is an important decision but it is a purely intellectual exercise, more like generating a wish list. Once adopted, the next hurdle is to provision for the hardware that implements the wish list, that is, the produce the processor’s microarchitecture. Once a microarchitecture designed is agreed upon, one needs to ensure that a fabrication process is in place and capable of producing the microarchitecture that implements the ISA."

A new version of the document has been uploaded.
Dan
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f13-759-lzheng23

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Unread post Thu Sep 12, 2013 10:37 pm

Re: Primer: Elements of Proc. Architecture. The H/S Interpla

Hi professor and my classmates,

After reading this consise and illustrated Primer, I learned a lot of things about the High-Performance-Computing. The following are the key points
1: There is important connection between software and hardware, and we can do some work in both aspects to speed up computing.
2: The hardware is made form basic to complex like the following way: Transistor->Gates->Logic Unit\Mux->Complex Combination Block->Array of Logic Elements.
3: FDX process is the way the hardware computes the data source.


I also want to try my best to promote professor`s Primer:
Typos:
Page 4: There are individuals who took a C, C++… ( took-->take)
Page 6: This is represents version 0.1 of this primer. (delete "is")
Page 8: The collection of instructions a processors is expected to know how to carry out is called its instruction set and along with… (hard to understand the first time to read, will be better to add "that" between "instructions" and "a processor")
Page 16: in reality there are more efficient ways to implementing NOR and NAND (implementing-->implement)
Page 18: There are also a number of registers tied to the task of handling function (subroutine) calls and their meaning will further clarified when discussing the memory model (clarified--> be clarified)

Suggestions:
if we can add some pictures in 1.2.5 The Bus and 1.2.6 Execution Pipelining, the reader will gain a better and vivid understanding of the thing the section is talking about



Lixing
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Dan Negrut

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Unread post Fri Sep 13, 2013 11:04 am

Re: Primer: Elements of Proc. Architecture. The H/S Interpla

Hi Lixing - thanks a lot for the feedback :-)

Took care of all of them except the one at page 4 and also the two pics, don't have the bandwidth to do it right now. I plan to do this in the future though.
A new version of the primer has been updated on the class website.

I very much appreciate you taking the time to provide feedback.

Thank you,
Dan
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f13-759-yarya

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Unread post Fri Sep 13, 2013 4:06 pm

Re: Primer: Elements of Proc. Architecture. The H/S Interpla

This might seem like splitting-hairs, may be, but there's an error that might confuse people who are new to MIPS.

Page 8, Figure 1: quote "Format of a processor instruction of type I for the MIPS ISA. There are two more formats for MIPS
instructions: type I; i.e., R-format from “register”, and J-type from “jump”."

That should be type R, not Type I.
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f13-759-yarya

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Unread post Fri Sep 13, 2013 4:08 pm

Re: Primer: Elements of Proc. Architecture. The H/S Interpla

Page 19: Quote "Global Pointer (gp) – a register that holds an address that points to the middle of a block of
memory in the static data segment. The static data segment is the portion of the main memory
that stores static variables"

Might be a good idea IMHO to mention that static variables are global variables, and thus the name of the pointer.
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Dan Negrut

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Unread post Sat Sep 14, 2013 9:17 am

Re: Primer: Elements of Proc. Architecture. The H/S Interpla

Hi Yash - i took both your suggestions.
splitting hairs is good.
a new version has been updated.
thank you,
Dan
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f13-759-pkgupta3

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Unread post Sat Sep 14, 2013 3:26 pm

Re: Primer: Elements of Proc. Architecture. The H/S Interpla

Hey Prof Dan,
I think a block diagram showing the Memory Hierarchy in terms of SRAM,DRAM and disk in the order of their peripheral distance from the processor must also be included in your updated version because it will prove helpful to get a better idea about the location of both SRAM and DRAM from the processor though we are able to get an idea from what is being shown in Fig. 13 and section 1.5.1 which follows the figure but still I think including the figure will better co relate the 'SRAM-DRAM-Magnetic Disk-Processor' cycle.
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Dan Negrut

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Unread post Sun Sep 15, 2013 9:59 am

Re: Primer: Elements of Proc. Architecture. The H/S Interpla

Thanks for the suggestion - it'll have though to wait like most suggestions calling for pictures.
Generating a new image places a heavy burden on me at a time when i have limited bandwidth.
That being said, all suggestions are very welcome, just that i won't be able to act on all of them right away.
Thank you, keep the suggestions coming...
Dan
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Unread post Tue Sep 17, 2013 10:35 pm

Re: Primer: Elements of Proc. Architecture. The H/S Interpla

Hi prof Dan,
The primer is very detailed and informative. :)

I found an error in page 41 , Sidebar 3 . The second last sentence
"The L2 cache is eight way associative while the L3 cache is 64 way associative". The L3 cache should be 16 way associative instead of 64 according to me.
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